This invention relates to data processing systems in which multiple data processing modules are inter-coupled to each other over a time-shared bus; and more particularly, it relates to methods and apparatus by which two of the modules in such a system share in the execution of commands which are sent to them over the bus.
In the prior art, data processing systems have been disclosed in which one module A sends commands over a bus to two other modules B and C for execution. However, a difficulty arises when module A sends the same command to both of the other modules B and C simultaneously, and only one of the modules B or C is permitted to execute that command. In that case, some method and apparatus is needed to insure that the command is executed by one, but not both, of the modules B and C.
Previously, the above problem was solved by providing a memory module on the bus and providing the bus with the ability to perform a Read-Modify-Write operation. This memory module stored a respective flag for each command; and, each of the modules B and C used the Read-Modify-Write operation to read, test, and modify the flags such that each command was performed by a just one module B or C.
Suppose, for example, that module B sought to execute a command. In that case module B initiated the Read-Modify-Write by sending a message to the memory which identified the particular command that was to be executed. In response on the next bus cycle, the memory sent an internally stored flag back to module B which indicated whether or not module C has already started the execution of that command. If the flag indicated that module C had not begun to execute the command, then on the next bus cycle, module B sent a modified flag back to the memory where it replaced the initially read flag. This modified flag indicated that module B would perform the command.
Likewise, module C could initiate the Read-Modify-Write operation in the same fashion. In that case, on the first bus cycle, module C sent a message to the memory which identified the command that was to be executed. In response, on the second bus cycle, the memory sent an internally stored flag back to module C which indicated whether or not module B has already started the execution of the command. Then, if module B has not started to perform the command, module C on the third bus cycle sent a modified flag back to the memory for storage therein which indicated that module C would perform the command.
One drawback, however, with the above described Read-Modify-Write operation is that it requires three consecutive bus transactions or bus cycles. Consequently, the Read-Modify-Write operation is relatively slow in comparison to a single cycle bus operation, such as the sending of one message on the bus from module B to module C.
Another drawback is that during the three bus cycles of a Read-Modify-Write, only one module B or C, together with the memory can use the bus. However, for some particular data processing systems, being locked off of the bus for three consecutive bus cycles is not tolerable.
Still another drawback is that in many existing data processing systems, the bus is unable to perform a Read-Modify-Write (i.e.--the bus does not have the ability to lock out all modules except one for three consecutive bus cycles). Thus, for those systems, the modules B and C which share in the execution of a command cannot be added to the system as an upgrade.
Accordingly, a primary object of the present invention is to provide a novel method and control circuit by which two modules on a time-shared bus share in the execution of a command without requiring any Read-Modify-Write operation.
Also, another object of the present invention is to provide a method and control circuit by which two modules on a time-shared bus share in the execution of a command by requiring only a single bus transaction or bus cycle between those modules.